Application of the hottest AD converter AD6644 in

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The application of a/d converter AD6644 in software radio

Abstract: AD6644 is a high-speed, high-performance monolithic 14 bit analog-to-digital converter, which contains a sample and hold circuit and a reference source. It can accurately transform broadband analog signals (200MHz input bandwidth), and has the characteristics of low noise (24dB) and low distortion (100dbsfdr). Its sampling rate can reach 65msps, and the typical value of signal-to-noise ratio is 74dB. This paper introduces the main characteristics and working principle of AD6644, and gives the application circuit of realizing high-speed multi bit sampling in software radio receiving system with AD6644

Keywords: a/d conversion; Data collection; Software radio; AD6644

in the construction of software radio, a/d and d/a play a key role. Generally, the a/d converter is required to have sufficient working bandwidth (above 2GHz) and high sampling rate (generally above 60MHz), and at the same time, there should be high a/d conversion bits to improve the dynamic range. The new generation a/d converter AD6644 introduced by ad company can meet its requirements. The characteristics, principles and applications of AD6644 devices will be introduced below

1 main features

the main features of the chip are as follows:

● the sample rate can be maintained at 65Mhz

● adopt full differential analog input

● in order to facilitate the interface with digital ASIC, the digital output stage can work on + 3.3V power supply

● including reference voltage source and tracking/holding amplifier

● small surface mount 52 pin package (LQFP) is adopted

ad6644's internal circuit structure is shown in Figure 1. The main limit parameters are listed in Table 1. Figure 2 shows the pin arrangement, and the function description of each pin is as follows:

DVCC: + 3.3V power output stage power supply (digital)

g color bright Nd: grounding terminal

vref:2.4v internal reference voltage. Apply 0.1 when using μ F slice capacitor bypass to the ground

encode: code input. Start converting data at the rising edge

encode complementary end, which can form a differential drive with encode

avcc: +5v analog power supply. Ain: analog input

ain: analog input complementary terminal

c1 ~ C2: internal offset point. Application 0.1 μ F slice capacitor bypass to the ground

dnc: no connection

ovr: over rated positioning, high indicating analog input exceeds ± FS

dmid: median value of output data voltage; Approximately equal to (DVCC)/2

d0 ~ D13: data output bits, where d0 is the least significant bit LSB and D13 is the most significant bit MSB

dry: data output preparation

2 working principle

ad6644 adopts a three-level sub area conversion structure. This design not only ensures the required conversion accuracy and speed, but also reduces power consumption and module size. The analog signal input mode of AD6644 is differential structure, and the voltage range of each input is centered on 2.4V, and the up and down swing is within 0.55v. Since the phase difference between the two inputs is 180 °, the maximum peak to peak value of the analog input signal is 2.2V

as can be seen from Figure 1, the two analog inputs are buffered first, and then enter the first sample holder (Th1). When the sampling clock is high, Th1 enters the hold state. The hold value of Th1 is used as the input of coarse 5-bit a/d converter (ADC1), and its output is used to drive a 5-bit d/a converter (dac1). If the delayed analog signal is subtracted from the output of dac1, a first residual signal can be generated at the input of the holder th3. The function of holder Th2 is to compensate for an analog channel delay after the digital delay of ADC1. The first residual signal is used for the second stage of conversion, which includes a 5-bit a/d conversion (ADC2), 5-bit d/a conversion (DAC2) and channel th4. Subtracting the first residual signal held by th4 from the quantized output of DAC2, the resulting second residual signal can be used as the input of th5

add ADC1, ADC2 and adc3, and transmit the corrected result to the digital error correction logic to output the final 14 bit analog-to-digital conversion result

Figure 3 shows the timing diagram of AD6644

3 application of AD6644

software radio is a new radio technology produced with the rapid development of computer and microelectronics technology in recent years. Its emergence is the product of three changes in radio communication from analog to digital, from fixed to mobile, from hardware to software. The concept of "software radio" was first clearly put forward by jeo mitola at the annual conference of the national communication system in May, 1992. It is a new generation of radio communication system developed by connecting modular and standardized hardware units in the form of bus to form a basic platform, and then realizing various wireless communication functions (including different frequency bands and different systems) through software loading, and putting a/d and d/a (analog/digital and digital/analog conversion) functions as close as possible to the antenna end. Therefore, software radio system has many advantages, such as openness, modularity, standardization, flexible implementation, software upgrading, and suitable for large-scale manufacturing. These characteristics make it not only begin to be applied in military and civil wireless communication, but also are being promoted to other wireless technology fields. Therefore, the research of this technology has quietly become a hot spot for countries to study the distance between markings

at present, on a/d and d/a devices, some products can work in the intermediate frequency band. AD6644 is an analog-to-digital converter with excellent performance, 14 bit resolution and 65msps sampling rate. It is the third generation of broadband ADC family after ad9042 (12 bit, 41msps) and AD6640 (12 bit, 65msps), but all shareholders will also participate in it. The software radio equipment using AD6644 is small in size, low in cost, and easy to program and set up for the new wireless service standard. Other features of AD6644 include less than 300fs sampling jitter and less than 1.3W power consumption. Therefore, the emergence of AD6644 provides an analog-to-digital converter with the best performance in the industry for the realization of a new generation of communication equipment K programmable digital radio receiver (commonly known as software radio)

there are many digital receivers using AD6644 as an analog-to-digital converter (ADC). Figure 4 shows the structural block diagram of a two channel digital receiver. The receiver gives full play to the performance of the AD6644, can well achieve broadband high-speed multi bit sampling, and can ensure a high sampling rate. The analog input bandwidth of its single ended ADC is 400MHz, the input impedance is 1K Ω, and differential input is adopted. The maximum sampling rate of ADC in the receiver can reach 65msps, and the maximum dynamic range can reach 137db


1.ad6644 14 bit, 40 msps/65 mspsa/dconverterta sheet.analog devices

2. Liu Shuming, Liu Bin. High performance analog-to-digital and analog converter devices. Xi'an University of Electronic Science and Technology Press, 2000.1 (end)

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