Application of the hottest AD9856 frequency conver

  • Detail

Application of AD9856 frequency converter in radar echo simulator

radar echo simulation is of great significance in the design, improvement and finalization of radar system. AD9856 is a quadrature digital up converter produced by Adi in the United States. It is internally integrated with a high-speed direct digital frequency synthesizer (DDS), a 12 bit high-speed, high-performance digital to analog converter, clock frequency multiplier circuit, digital filter and other digital signal processing function modules. It has the advantages of low cost, low power consumption, small size, large dynamic range and so on. It can process the formed baseband sampling value sequence from DSP, up convert it into if, and generate if analog signal of radar echo. AD9856 can be used in communication and radar systems

2 the working principle of AD9856

2.1 the basic functions of AD9856

ad985 and based on the advantages of the concentration area itself and the characteristics of the aluminum based new material industry 6 the basic characteristics and technical indicators are as follows:

● +3v single power supply

● output bandwidth from DC to 80MHz

● have sf-dr greater than 52dB at 40MHz output frequency, SFDR greater than 48dB at 70MHz output frequency, and narrowband SFDR greater than 80dB at 70MHz output frequency

● interpolation filter with programmable sampling rate

● programmable reference clock frequency multiplier

● built in sinx/x compensation filter

● have bidirectional control bus interface

● support burst and continuous TX modes

● single frequency mode can be used for direct frequency synthesis

2.2 the principle of AD9856 and the functions of each part

(1) data composition and serial parallel conversion

the structure of AD9856 is shown in Figure 1. The internal data format of AD9856 is a 12bit binary complement. The I and Q2 data of baseband signal are input alternately. The data multiplexer needs to identify the input data, convert it into I and Q2 parallel data streams, and send it to the next level circuit

(2) half band filter (HBF)

half band filter (HBF) is divided into three levels: hbfl, hbf2 and hbf3. Among them, hbfi is a 47 order filter, hbf2 is a 15 order filter, the joint interpolation loss of the first two stages of HbF is only 0.01dB, and hbf3 is an optional 11 order filter, with a signal loss of 0.03db. Each level of HbF can double the sampling rate of the data. In order to make the signal band in the flat part of the filter passband, it is necessary to significantly lower the new output energy of 4million ~ 430 tons from 2013 to 2014, and improve the cut-off frequency of HbF, that is to say, the data should be sampled before being input into AD9856

(3) CIC of cascade integral comb filter

ad9856 is actually a programmable oversampling filter, and the range of oversampling rate is 2 ≤ R ≤ 63. With the change of R, CIC will introduce different insertion losses. To make up for this loss. The user can set the CIC gain bit to double the CIC output. However, in this working mode, it must be ensured that the output signal will not overflow

(4) quadrature modulation

ad9856 quadrature modulation is to move the spectrum of baseband signal to the required carrier frequency, which is commonly referred to as up conversion. The cosine and sine digital carriers required for quadrature modulation are generated by a high-speed direct digital signal synthesizer (DDS), and its frequency can be controlled by setting corresponding registers. These two digital carriers are multiplied by the I and Q data output by CIC respectively, and then added or subtracted to obtain the modulated digital intermediate frequency signal. The sampling rate of I and Q data output by CIC is the same as that of DDS digital carrier, that is, the system clock sampling rate (sysclk) of AD9856. Therefore, the modulated signal is actually a group of data streams with a sampling rate of sysclk

(5) d/a conversion

the modulated digital signal should be converted into an analog signal through a 12 bit DAC. DAC realizes D/a conversion through zero order hold. Due to the zero order hold effect, the spectrum of its output signal is actually weighted by sinc envelope. Therefore, it is necessary to add an anti sinc filter (ISF) in front of the DAC to process the input data stream to correct the distortion caused by the sinc envelope. The D/a conversion will generate interference signals at n * sysclk ± fcarrier (n=1, 2, 3), which can be filtered out by an external RLC filter. Generally, a 7th order elliptic low-pass filter is sufficient. AD9856 provides two complementary current outputs. The output can be set through its 25 pin DAC RSET because the full value IOUT range of the current controlled by a single-chip computer is 5mA ~ 20mA. Its relationship provides a flexible synchronous serial communication interface for rset=39.936/iout

(6) control unit

ad9856, which can read and write all registers of AD9856. The control unit sets the working mode of AD9856 according to the contents of each register. AD9856 also provides an interface for serial communication with ad8320 (programmable cable drive amplifier). The control unit can directly set the gain of ad8320 through this serial port

(7) input data mode

ad9856 provides two timing modes of input data: burst mode and continuous mode. In burst mode.Ad9856 is synchronized with the input data through the rising edge of txenable. Burst mode can be used to make sutures (biosyn reg;) All three word lengths (12bit, 6bit and 3bit) are supported. For continuous mode, txenable can be regarded as the input data clock. In addition to being used for synchronization, this signal can also indicate whether the input data is channel I or channel Q (1 indicates channel I, O indicates channel q). Continuous mode only supports 12bit word length

Fig. 2 and Fig. 3 respectively show the timing relationship of the two input modes, in which internal I and internal Q are parallel I and Q data streams generated by data separation

3 application in PD radar echo simulator

3.1 hardware composition

this system is composed of ADI's qdu AD9856, DGA ad8369, tsl01 DSP and Altera's ep1k30 FPGA. The structural block diagram is shown in Figure 4

in Figure 4, TS101 generates orthogonal I and Q2 channel radar echo data, and tsl0l passes

Copyright © 2011 JIN SHI